Video apparatuses need stable synchronizing signals having a small period variation to display or record images. However, when radio waves received in an antenna are weak or when channel changing is made, a period of synchronizing signals can be disturbed temporarily. In addition, since false synchronizing signals such as equalizing pulses and cut-in pulses having frequencies which are integral multiples of the frequency of horizontal sync signals are included in each vertical retrace interval in order to ensure the continuity of the horizontal sync signals, a phase of reproduced synchronizing signals can shift abruptly at a switching point of a video head during video reproduction by a VCR. In order to avoid image quality degradation due to phase disturbance of synchronizing signals, a synchronizing signal processing circuit capable of correcting phase disturbance of incoming synchronizing signals is used to obtain synchronizing signals having a stable period.
FIG. 11 shows a structure of a horizontal sync signal processing circuit disclosed in Japanese Patent Publication No. 7-89653. This horizontal sync signal processing circuit includes an input terminal 20 for receiving horizontal sync signals, a noise eliminating circuit 21 for eliminating noises comprised of narrow pulses included in the horizontal sync signals entering at the input terminal 20, a timing pulse producing circuit 22 for producing timing pulses having a predetermined period on the basis of the output of an after-described mask circuit 25, a free-running synchronizing pulse producing circuit 23 for producing free-running synchronizing pulses when there are missing horizontal synchronizing signals on the basis of the outputs of the timing pulse producing circuit 22 and the mask circuit 25, a mode determination circuit 24 for determining an operation mode on the basis of outputs of the noise eliminating circuit 21, the free-running synchronizing pulse producing circuit 23, and the mask circuit 25, a synchronizing pulse producing circuit 26 for producing synchronizing pulses on the basis of the outputs of the free-running synchronizing pulse producing circuit 23 and the mask circuit 25, and an output terminal 27. The mask circuit 25 is for passing or blocking horizontal sync signals output from the noise eliminating circuit 21 by controlling its gate on the basis of the outputs of the timing pulse producing circuit 22 and the mode determination circuit 24.
The operation of the horizontal sync signal processing circuit having the structure as shown in FIG. 11 will be explained below. Here, assume that horizontal sync signals are negative-going pulse signals, that is, pulse signals of L (Low) level having a certain pulse width. The noise eliminating circuit 21, which includes a 4-bit shift register driven by a clock having a stable period produced by a quartz oscillator for example, brings its output to H (High) level only when the first two stages of the 4-bit shift register are at the L level and the last two stages of the register are at the H level. Thus, a noise pulse having a width shorter than a 2-clock period can be eliminated. When the output of the noise eliminating circuit 21 rises to the H level, it is meant that a falling edge or reference edge of a horizontal sync signal has been detected.
The timing pulse producing circuit 22 has a first counter which counts the above-described clock having a stable period, that is, a counter which is incremented by 1 each time a clock pulse is input. This first counter is reset when the output of the mask circuit 25 rises to the H level or when its count value reaches a predetermined first value. The first value is equivalent to a horizontal scanning period, that is, a period of the horizontal sync signals. Accordingly, the first counter is reset without exception when its count value reaches the value equivalent to the horizontal scanning period at most. When the count value of the first counter reaches the first value, the timing pulse producing circuit 22 resets the first counter and also produces a timing pulse and supplies it to the self-running synchronizing pulse producing circuit 23. In addition, the timing pulse producing circuit 22 produces another timing pulse and supplies it to the mask circuit 25 when the count value of the first counter reaches a second value equivalent to a time period that is slightly shorter than the horizontal scanning period. Here, the second value is equivalent to a time period which is shorter than the horizontal period by 5%. Accordingly, the timing pulse producing circuit 22 outputs a timing pulse to the mask circuit 25 when the count value of the first counter reaches a value equivalent to 95% of the horizontal scanning period.
The self-running synchronizing pulse producing circuit 23 includes a second counter. This second counter starts to count the clock in response to the timing pulse output from the timing pulse producing circuit 22, and stops the counting when the output of the mask circuit 25 rises to the H level or when its count value reaches a predetermined third value. Here, the third value is equivalent to 5% of the horizontal scanning period. The self-running synchronizing pulse producing circuit 23 produces a self-running synchronizing pulse when the count value of the second counter reaches the third value, and supplies it to the mode determination circuit 24, the mask circuit 25, and the synchronizing pulse producing circuit 26. Accordingly, if the self-running synchronizing pulse producing circuit 23 receives the timing pulse from the timing pulse producing circuit 22, it produces a self-running synchronizing pulse after a lapse of a time equivalent to 105% of the horizontal scanning period after the first counter starts to count the clock.
The mode determination circuit 24 includes a state machine which can be in either one of a synchronous state and a self-running state, and an octal counter. The state machine inverts its state each time the octal counter counts up to 8. When the state machine is in the synchronous state, the octal counter increases its count value by one each time a false synchronizing pulse or a self-running synchronizing pulse produced by the self-running synchronizing pulse producing circuit 23 is input, and resets its count value to zero each time a true synchronizing pulse is input. On the other hand, if the state machine is in the self-running state, the octal counter resets its count value to zero each time a false synchronizing pulse or a self-running synchronizing pulse is input, and increases its count value by one each time a true synchronizing pulse is input. Accordingly, the state machine changes from the self-running state to the synchronous state when eight true synchronizing pulses alone enter the state machine consecutively, and changes from the synchronous state to the self-running state when eight false or self-running synchronizing pulses alone enter the state machine consecutively. The state of the state machine is output to the mask circuit 25. Discrimination between the true synchronizing pulse and the false synchronizing pulse can be made from the state of a gate within the mask circuit 25 at the instant when the output of the noise eliminating circuit 21 rises to the H level, or a falling edge of an incoming synchronizing signal is detected. To be more specific, a pulse output from the noise eliminating circuit 21 when the gate within the mask circuit 25 is open is a true synchronizing pulse, while a pulse output from the noise eliminating circuit 25 when the gate within the mask circuit 25 is closed is a false synchronizing pulse.
The mask circuit 25 has a device for producing a gate signal by which the closing and opening of the gate within the mask circuit is controlled. The gate signal produced by this device is at the H level until the output of the gate rises to the H level after the mask circuit 25 receives a timing pulse from the timing pulse producing circuit 22 to open the gate, while it is at the L level at other times to close the gate. If the gate signal is at the H level, the output of the noise eliminating circuit 21 becomes the output of the gate. On the other hand, if the gate signal is at the L level, the output of the gate is kept at the L level irrespective of the output of the noise eliminating circuit 21. This gate signal is output to the mode determination circuit 24. The mask circuit 25 supplies the output of the gate to the timing pulse producing circuit 22, the self-running synchronizing pulse producing circuit 23, and the synchronizing pulse producing circuit 26 if the output of the mode determination circuit 24 indicates the synchronous state. On the other hand, they are supplied with the output of the noise eliminating circuit 21 if the output of the mode determination circuit 24 indicates the self-running state.
The synchronizing pulse producing circuit 26 outputs horizontal sync signals having a desired pulse width from the output terminal 27 by keeping its output at the L level for a predetermined time period after the moment at which the output of the mask circuit 25 is brought to the H level or after the moment at which the self-running synchronizing pulse producing circuit 23 produces a self-running synchronizing pulse.
FIGS. 12, 13 and 14 are timing charts showing waveforms of horizontal sync signals entering at the input terminal 20, gate signals in the mask circuit 25, self-running synchronizing pulses produced by the self-running synchronizing pulse producing circuit 23, and horizontal sync signals outgoing from the output terminal 27. T0 in these FIGS. represents a period of the incoming horizontal sync signals.
FIG. 12 shows a case where incoming horizontal sync signal includes false synchronizing pulses of a short period. As long as the horizontal sync signals are input at regular intervals of T0, the gate is closed each time a horizontal sync signal is input until a time period equivalent to 95% of the horizontal scanning period elapses when the timing pulse producing circuit 22 produces a timing pulse. Therefore, false pulses of a short period are blocked by the gate, whereby disturbance of horizontal synchronization due to false pulses can be avoided.
FIG. 13 shows a case where horizontal sync signals entering at the input terminal 20 has an apparent period of 2T0 because one of them is lost. If a horizontal sync signal is not detected while the gate is open, the self-running synchronizing pulse producing circuit 23 produces a self-running synchronizing pulse after a lapse of a time period equivalent to 105% of the horizontal scanning period after the last synchronizing pulse is input. It is possible to avoid disturbance of horizontal synchronization by outputting this self-running synchronizing pulse as a horizontal sync pulse by way of the synchronizing pulse producing circuit 26.
FIG. 14 shows a case where horizontal sync signals cease entering at the input terminal 20 at some point in time. In this case, a first self-running synchronizing pulse is produced after a lapse of a time period equivalent to 105% of the horizontal scanning period after the last synchronizing pulse is input. On the other hand, a second and subsequent self-running synchronizing pulses are produced at intervals of T0 which is equal to the original horizontal scanning period, since the first counter within the timing pulse producing circuit 22 is reset at intervals of T0.